Kind of a wild idea, but have you considered using this as a markup language for logic diagrams? I'm thinking something like mermaid - https://mermaid.js.org/ While this might not be super useful for chip design, it is a fully functional HDL, and since it is gate level, it would map nicely to diagrams.
If you are just interested in a structural description (so-called netlist) the standard is EDIF.
You've reinvented Verilog primitive gates.
I'm sure you didn't mean to, but this comes across as a shallow dismissal, which is against the site guidelines (https://news.ycombinator.com/newsguidelines.html):
"Please don't post shallow dismissals, especially of other people's work. A good critical comment teaches us something."
... and particularly against the Show HN guidelines (https://news.ycombinator.com/showhn.html):